Dynamic random access memory device with low-power consumption column selector

ABSTRACT

A column selector of a dynamic random access memory device is implemented by a plurality of switching circuits for transferring a potential difference from a sense amplifier to a shared data line pair, and one of the switching circuits selectively discharge the data lines of the pair to a ground voltage line for transferring the potential difference to the shared data line pair, wherein a potential control circuit is coupled between the switching circuits and the ground voltage line for decreasing the current flowing from the data line to the ground voltage line after production of an output data signal, thereby decreasing the current consumption.

FIELD OF THE INVENTION

This invention relates to a dynamic random access memory device and,more particularly, to a dynamic random access memory device having alow-power consumption column selector for transferring a potentialdifference on a selected bit line pair to a data line pair.

DESCRIPTION OF THE RELATED ART

A typical example of the dynamic random access memory device isillustrated in FIG. 1 of the drawings, and the prior art dynamic randomaccess memory device largely comprises a first memory cell array 1, asecond memory cell array 2, an array of sense amplifier circuits SA1 toSAn shared between the first and second memory cell arrays 1 and 2, afirst transfer gate array 3 associated with the first memory cell array1, a second transfer gate array 4 associated with the second memory cellarray 2, a column selector 5 for selectively coupling the senseamplifier circuits SA1 to SAn through a data line pair DL to a dataamplifier circuit 6 and a charging circuit 7 for the data line pair DL.Although the prior art dynamic random access memory device furthercomprises a write-in circuit etc., FIG. 1 does not show these circuits,because they are less important for understanding problems inherent inthe prior art dynamic random access memory device.

The first memory cell array 1 is implemented by a plurality of memorycells for storing data bits in the form of potential difference, and thememory cells are indicated by small circles. A plurality of bit linepairs BLa1, BLa2, . . . and BLan are selectively coupled with theinput/output nodes of the memory cells, and word lines WLa are furtherselectively coupled to the control nodes of the memory cells. The wordlines WLa are selectively driven to an active level, and the stored databits are transferred from the associated memory cells to the bit linepairs BLa1 to BLan.

The second memory cell array 2 is also arranged. Namely, a plurality ofmemory cells form a matrix, and are selectively coupled to a pluralityof word lines WLb1/WLb2 and a plurality of digit line pairs BLb1, BLb2,. . . and BLbn. If one of the word lines such as WLb1 is energized, theassociated memory cells delivers the stored data bits to the bit linepairs, respectively.

The first transfer gate array 3 has a plurality of sets of n-channelenhancement type transfer transistors Qn1/Qn2 coupled between the bitline pairs BLa1 to BLan and the sense amplifier circuits SA1 to SAn, anda first transfer signal TG1 causes the n-channel enhancement typetransfer transistors Qn1/Qn2 to concurrently turn on for coupling thesense amplifier circuits SA1 to SAn to the digit line pairs BLa1 toBLan.

Similarly, a plurality of sets of n-channel enhancement type transfertransistors Qn3/Qn4 form the second transfer gate array 4, and a secondtransfer signal TG2 concurrently changes the n-channel enhancement typetransfer transistors Qn3/Qn4 between on-state and off-state so as tocouple the sense amplifier circuits SA1 to SAn to the digit line pairsBLb1 to BLbn.

The sense amplifier circuits SA1 to SAn are operative to rapidly developpotential differences at the input/output nodes thereof, and thearrangement of each sense amplifier is well know to a person skilled inthe art.

The column selector unit 5 comprises a plurality of switching circuits51 to 5n respectively associated with the sense amplifier circuits SA1to SAn, and each of the switching circuits 51 to 5n has a first parallelcombination of n-channel enhancement type switching transistors Qn5/Qn6coupled to the data line pair DL and a second parallel combination ofn-channel enhancement type switching transistors Qn7/Qn8 coupled betweenthe first parallel combination and a discharging line DSC. Columnaddress decoded signals Y1 to Yn are distributed to the switchingcircuits 51 to 5n, and the n-channel enhancement type switchingtransistors Qn5/Qn6 are gated by one of the column address decodedsignals Y1 to Yn. The gate electrodes of the n-channel enhancement typeswitching transistors Qn7 and Qn8 are coupled to the pair ofinput/output nodes of the associated sense amplifier circuit SA1, SA2, .. . or SAn. If the column address decoded signals Y1 to Yn enable theswitching circuit 51, the n-channel enhancement type switchingtransistors Qn5 and Qn6 turn on, and the input/output nodes of the senseamplifier circuit SA1 causes the n-channel enhancement type switchingtransistors Qn7/Qn8 to selectively turn on and off. As a result, one ofthe data lines of the pair DL is coupled through the switching circuit51 to the discharging line DSC, and the potential difference between theinput and output nodes of the sense amplifier circuit SA1 is relayed tothe data line pair DL.

The charging circuit 7 is implemented by a parallel combination ofp-channel enhancement type charging transistors Qp9 and Qp10, and thep-channel enhancement type charging transistors Qp9 and Qp10 are coupledbetween a power voltage line Vcc and the data lines of the pair DL. Thegate electrodes of the p-channel enhancement type charging transistorsQp9 and Qp10 are coupled to the drain nodes, and are maintained in theon-state at all times. For this reason, the data lines are charged to apredetermined level lower than the power voltage level Vcc by thethreshold of the p-channel enhancement type charging transistors Qp9 andQp10 before the column address decoded signals Y1 to Yn select one ofthe switching circuits 51 to 5n.

Assuming now that a data bit stored in the memory cell MCx is accessed,the bit line pairs BLa1 to BLan and BLb1 to BLbn have been alreadycharged to a precharge level. For the sake of simplicity, description ishereinbelow focused on the second memory cell array 2.

The row address bits are decoded, and the word line WLb1 is changed tothe active level. The memory cells coupled to the word line WLb1 deliverthe data bits to the associated bit line pairs BLb1 to BLbn,respectively, and produce potential differences on the associated bitline pairs BLb1 to BLbn, respectively.

The transfer signal TG2 is changed to the active high voltage level, andthe other transfer signal TG1 remains low. As a result, the n-channelenhancement type transfer transistors Qn3 and Qn4 turn on, and then-channel enhancement type transfer transistors Qn1 and Qn2 aremaintained in the off-state. Then, the potential differences on the bitline pairs BLb1 to BLbn are propagated to the sense amplifier circuitsSA1 to SAn, respectively.

The sense amplifier circuits SA1 to SAn are activated so as to rapidlydevelop the potential differences. The n-channel enhancement typetransfer transistors Qn3 and Qn4 are assumed to propagate a high voltagelevel and a low voltage level, respectively.

The column address decoded signal Y1 allows the n-channel enhancementtype switching transistors Qn5/Qn6 of the switching circuit 51 to turnon, and the other column address decoded signals keep the othern-channel enhancement type switching transistors Qn5/Qn6 of the otherswitching circuits 52 to 5n off. For this reason, the switching circuit51 becomes responsive to the potential difference supplied from thesense amplifier circuit SA1. The potential difference indicative of thedata bit read out from the memory cell MCx allows the n-channelenhancement type switching transistor Qn7 to produce a conductivechannel from the data line to the discharging line DSC and the othern-channel enhancement type switching transistor Qn8 to block the otherdata line from the discharging line DSC. As a result, the data linecoupled to the p-channel enhancement type charging transistor Qp9becomes lower than the other data line coupled to the p-channelenhancement type charging transistor Qp10.

In this instance, the column address decoded signal Y1 does not affectthe behavior of the switching circuit 51, and the column address decoder(not shown) can drive the column address decoded signals Y1 to Yn uponactivation of the sense amplifier circuits SA1 to SAn. This results inacceleration of the data access.

However, a problem is encountered in the prior art dynamic random accessmemory device in large current consumption. The large currentconsumption is derived from the selected switching circuit 51, 52, . . .or 5n continuously discharging the data line until the column addressdecoded signals selects another switching circuit. As a result, while anexternal device (not shown) is accessing data bits stored in the priorart dynamic random access memory device, current continuously flows fromone of the p-channel enhancement type charging transistors Qp9 and Qp10through the associated data line and the selected switching circuit tothe discharging line DSC.

The prior art dynamic random access memory device commercially availablehas more than one pair of memory cell arrays. For example, a memory cellarrays 11 to 1m and m+1 sense amplifier/column selector units 20 to 2mare alternately arranged as shown in FIG. 2. In order to decrease thecurrent consumption, the memory cell arrays 11 to 1m and the senseamplifier/column selector units 20 to 2m are partially activated for adata access. If the prior art dynamic random access memory deviceenables a quarter of the memory cells, the memory cell arrays 12, 16, .. . and the associated sense amplifier/column selector units 21, 22, 25,26, . . . are activated, and the activated memory cells and the senseamplifier/column selector units are hatched for better understanding.Although the bit line pairs of the activated memory cell arrays areprecharged before a data access, the other bit line pairs are notprecharged, and the dynamic random access memory device is expected todrastically decrease the current consumption.

However, a column address decoder 30 is shared between the columnselectors, and a substantial amount of current is consumed by theswitching circuits of the activated column selectors. Therefore, theproblem is serious for a dynamic random access memory device with alarge number of memory cell arrays.

If the column address decoder retards the selection of the switchingcircuits 51 to 5n, the current consumption is decreased. However, thedata access becomes slow.

SUMMARY OF THE INVENTION

It is therefore an important object of the present invention to providea dynamic random access memory device which is reduced in currentconsumption without sacrifice of data access speed.

To accomplish the object, the present invention proposes to varyresistance against current from a pair of second data lines.

In accordance with the present invention, there is provided asemiconductor memory device comprising: a) a plurality of addressablememory cells for storing data bits; b) a plurality pairs of first datalines selectively coupled to the plurality of addressable memory cells;c) a first addressing system for selectively connecting the plurality ofaddressable memory cells to the plurality pairs of first data lines; d)second data lines paired with each other; e) a charging circuit coupledto the second data lines for supplying current thereto; f) a dischargingline for discharging the current; g) a second addressing system having aplurality of switching circuits coupled in parallel between the seconddata lines and the discharging line, one of the plurality of switchingcircuits being responsive to a data bit on one of the plurality pairs offirst data lines for selectively connecting the second data lines to thedischarging line, thereby transferring the data bit to the second datalines in the form of potential difference; h) an interface responsive tothe data bit on the second data lines for producing a data signal; andi) a current control means coupled between the discharging line and avoltage source, and increasing the current flowing from the dischargingline to the voltage source for enlarging the potential differencebetween the second data lines before the interface produces the datasignal, the current control means decreasing the current aftercompletion of the production of the data signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the dynamic random access memory deviceaccording to the present invention will be more clearly understood fromthe following description taken in conjunction with the accompanyingdrawings in which:

FIG. 1 is a circuit diagram showing the arrangement of the prior artdynamic random access memory device;

FIG. 2 is a block diagram showing the arrangement of the prior artdynamic random access memory device commercially available;

FIG. 3 is a circuit diagram showing the arrangement of a dynamic randomaccess memory device according to the present invention; and

FIG. 4 is a timing chart showing an access to a data bit stored in thedynamic random access memory device.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 3 of the drawings, a dynamic random access memorydevice embodying the present invention is fabricated on a singlesemiconductor chip 31, and memory cell arrays 32a and 32b areincorporated in the dynamic random access memory device. The memory cellarrays 32a and 32b are paired with each other for forming an array pair.The memory cell array 32a is implemented by a plurality of memory cellsMA11, MA12, . . , MA21, MA22, . . . , MAm1, MAm2, . . . arranged inmatrix, and the other memory cell array 32b is also implemented by aplurality of memory cells MB11, MB12, . . . , MB21, MB22, . . . , MBm1,MBm2 arranged in matrix. An n-channel enhancement type switchingtransistor (not shown) and a storage capacitor (not shown) coupled inseries forms each of the memory cells MA11 to MAm2 and MB11 to MBm2.Although more than one array pair is incorporated in the dynamic randomaccess memory device, the other array pairs are not shown in FIG. 3 forthe sake of simplicity.

A plurality of bit line pairs BL1, BL2, . . . and BLm are shared betweenthe memory cell arrays 32a and 32b, and the bit lines of each pair arelabeled with BLa and BLb. Each bit line pair BL1/BL2/BLm is split into aleft section, an intermediate section and a right section, and the leftsections and the right sections are respectively assigned to the memorycell array 32a and the memory cell array 32b. The lines of memory cellsMA11/MA21/MAm1 . . . , MA12/MA22/MAm2 . . . of the array 32a arealternately coupled to the bit lines BLa and the bit lines BLb, and thebit lines BLa and the bit lines BLb are further coupled to the lines ofmemory cells MB11/MB21/MBm1 . . . , and MB12/MB22/MBm2 . . . in theright sections. Thus, the bit line pairs BL1 to BLm are shared betweenthe memory cell arrays 32a and 32b, and data bits are propagated throughthe left or right sections between the intermediate sections and thememory cell array 32a or 32b in the form of potential difference.Although precharge/balancing circuits are coupled to the left sectionsand the right sections for balancing the bit line pairs at a prechargelevel before read-out of the data bits from selected memory cells, theprecharge/balancing circuits are not shown in FIG. 3.

The dynamic random access memory device according to the presentinvention further comprises a plurality sets of word lines WLa1/WLa2 andWLb1/WLb2 respectively associated with the memory cell arrays 32a and32b for selectively coupling the memory cells MA11 to MAm2 and MB11 toMBm2 to the associated bit lines BLa and BLb. The word lines WLa1 andWLa2 are respectively associated with the lines of memory cellsMA11/MA21/MAm1 . . . , MA12/MA22/MAm2, . . . , and the n-channelenhancement type switching transistors of the memory cells areconcurrently gated by the associated word lines WLa1 and WLa2.Similarly, the word lines WLb1 and WLb2 are respectively associated withthe lines of memory cells MB11/MB21/MBm1, . . . and MB12/MB22/MBm2, . .. , and the n-channel enhancement type switching transistors of thememory cells concurrently turn on in the presence of the active highvoltage level on the associated word line WLb1 or WLb2. Though not shownin FIG. 3, the word lines WLa1/WLa2 and WLb1/WLb2 are selectivelyenergized by a row-address decoder/word line driver unit.

The dynamic random access memory device further comprises a firsttransfer gate array 33a coupled between the left sections and theintermediate sections, a second transfer gate array 33b coupled betweenthe right sections and the intermediate sections, an array of senseamplifier circuits SA1, SA2, . . . and SAn and a column selector or anarray of switching circuits 341, 342, . . . and 34m coupled between apair of data lines DL1/DL2 and a discharging line DSC.

The first transfer gate array 33a has a plurality pairs of n-channelenhancement type switching transistors Qn11/Qn12 coupled between theleft sections and the intermediate sections, and the n-channelenhancement type switching transistors Qn11/Qn12 are responsive to afirst gate control signal TG1 for electrically connecting the leftsections to the intermediate sections.

The second transfer gate array 33b has a plurality pairs of n-channelenhancement type switching transistors Qn13/Qn14 coupled between theright sections and the intermediate sections, and the n-channelenhancement type switching transistors Qn13/Qn14 are concurrently gatedby a second gate control signal TG2 for electrically connecting the leftsections to the intermediate sections. Though not shown in FIG. 3, thefirst gate control signal and the second gate control signal areselectively produced by a timing controller, and either memory cellarray 32a or 32b becomes accessible.

The sense amplifier circuits SA1 to SAm develop the potentialdifferences on the intermediate sections of the bit line pairs BL1 toBLm through differential amplification so as to rapidly discriminatingthe logic level of the data bits.

The switching circuits 341 to 34m are similar in circuit arrangement toone another, and each switching circuit comprises a parallel combinationof n-channel enhancement type switching transistors Qn15/Qn16 coupled atthe source nodes thereof to the data lines DL1 and DL2 and a parallelcombination of n-channel enhancement type switching transistorsQn17/Qn18 coupled between the n-channel enhancement type switchingtransistors Qn15/Qn16 and the discharging line DSC.

The switching circuits 341 to 34m are selectively enabled with columnaddress decoded signals Y1, Y2, . . . and Ym, and the n-channelenhancement type switching transistors Qn15/Qn16 of the enabledswitching circuit turn on for electrically connecting the data lines DL1and DL2 to the associated n-channel enhancement type switchingtransistors Qn17/Qn18.

The switching circuits 341 to 34m are associated with the bit line pairsBL1 to BLm, and the n-channel enhancement type switching transistorsQn17 and Qn18 of each switching circuit are gated by the bit lines BLaand BLb of the associated bit line pair. The bit lines BLa and BLb ofeach pair propagates a potential difference indicative of a data bit tothe associated sense amplifier circuit so that the n-channel enhancementtype switching transistors Qn17 and Qn18 selectively turn on and off.One of the n-channel enhancement type switching transistors Qn17 andQn18 couples the associated data line to the discharging line DSC.However, the other of the n-channel enhancement type switchingtransistors Qn17 and Qn18 is turned off, and isolates the associateddata line from the discharging line. As a result, a potential differencetakes place between the data lines DL1 and DL2, and the potentialdifference on the bit line pair is transferred through the switchingcircuit to the data lines DL1 and DL2.

The dynamic random access memory device according to the presentinvention further comprises a charging circuit 35 implemented by aparallel combination of p-channel enhancement type charging transistorsQp21 and Qp22. The p-channel enhancement type charging transistors Qp21and Qp22 are coupled between a power voltage line Vcc and the data lineDL1 and DL2, and the gate electrodes of the p-channel enhancement typecharging transistors Qp21 and Qp22 are coupled to the drain nodesthereof. The p-channel enhancement type charging transistors Qp21 andQp22 thus arranged supply current to the data lines DL1 and DL2, andkeep the potential level at the data lines DL1 and DL2 at a certainlevel lower than the power voltage level by the threshold thereof in sofar as the data lines DL1 and DL2 are isolated from the discharging lineDSC.

The dynamic random access memory device according to the presentinvention further comprises an output circuit 36 coupled between thedata lines DL1 and DL2 and a data terminal, and the output circuit 36produces an output data signal Dout from the potential difference on thedata lines DL1 and DL2. In this instance, the output circuit 36 servesas an interface. Although a write-in circuit is further incorporated forwriting a data bit into one of the memory cells MA11-MAm2 and MB11-MBm2,the write-in circuit is not shown in FIG. 3.

The dynamic random access memory device according to the presentinvention further comprises a potential control circuit 37 serving as acurrent control means. The potential control circuit 37 comprises twon-channel enhancement type discharging transistors Qn31 and Qn32 coupledin parallel between the discharging line DSC and a ground line GND.

The gate electrode of the n-channel enhancement type dischargingtransistor Qn31 is coupled to the discharging line DSC, and then-channel enhancement type discharging transistor Qn31 is turned onwhile the discharging line is higher than the threshold thereof.However, if the discharging line DSC reaches the threshold level of then-channel enhancement type discharging transistor Qn31, the n-channelenhancement type discharging transistor Qn31 turns off, and isolates thedischarging line DSC from the ground line GND. Thus, the n-channelenhancement type discharging transistor Qn31 serves as a diode.

A potential control signal CV is supplied to the gate electrode of then-channel enhancement type discharging transistor Qn32, and is suppliedfrom the timing generator (not shown). The timing generator produces notonly the control signals TG1/TG2/CV but also various control signalssuch as a precharge control signal for the precharging circuits (notshown), an activation signal for the sense amplifier circuits SA1 to SAmand an output enable signal for the output circuit 36.

The dynamic random access memory device thus arranged selectively entersinto a read-out phase for a data access, a write-in phase for rewritingthe data bits in the memory cells and a refreshing phase for maintainingthe data bits in the memory cells. The circuit behaviors in the write-inphase and the refreshing phase are analogous to those of the prior art,and no description is incorporated hereinbelow. For this reason,description on the circuit behavior is focused on the read-out phasewith reference to FIG. 4 of the drawings on the assumption that thememory cell MB11 is accessed. Each of the data bits are delivered to theexternal device through a single access cycle, and each access cycle isdivided into the first period T1 and the second period T2.

Although the data bits stored in the memory cell array 32a aresimultaneously read out onto the left sections of the bit line pairs BL1to BLm, no description is made on these data bits for the sake ofsimplicity.

An external device is assumed to supply address bits indicative of theaddress assigned to the memory cell MB11, and the first period T1 startsat time t1. The potential control signal CV is changed to the activehigh voltage level, and the n-channel enhancement type dischargingtransistor Qn32 turns on so as to pull down the discharging line DSC tothe ground voltage level.

The timing generator (not shown) changes the precharge control signal tothe active level, and the precharge circuits (not shown) charge andbalance the bit lines BLa and BLb. The timing generator keeps the gatecontrol signals TG1 and TG2 in the inactive low voltage level, and thefirst and second transfer gate arrays 33a and 33b isolate theintermediate sections from the left and right sections.

The row address decoder (not shown) changes the word line WLb1 to theactive high voltage level, and the data bits stored in the storagecapacitors in the form of electric charges produce potential differenceson the right sections of the bit line pairs BL1 to BLm. The timinggenerator changes the gate control signal TG2 to the active high voltagelevel, and keeps the other gate control signal TG1 in the inactive lowvoltage level. As a result, only the right sections are coupled to theintermediate sections, and the potential differences are transferred tothe intermediate sections.

The timing generator (not shown) activates the sense amplifier circuitsSA1 to SAm, and the sense amplifier circuits SA1 to SAm start to rapidlydevelop the potential differences transferred from the right sections ofthe bit line pairs BL1 to BLm.

The charging circuit 35 keeps the data lines DL1 and DL2 at the certainvoltage level, and the switching circuits 341 to 34m isolate the datalines DL1 and DL2 from the discharge line DSC. For this reason, thecurrent consumption I of the charging circuit 35 is zero.

The column address decoder (not shown) changes the column addressdecoded signal Y1 to the active high voltage level at time t2. However,the other column address decoded signals Y2 to Ym are maintained at theinactive low voltage level. The column address decoded signal Y1 allowsthe n-channel enhancement type switching transistors Qn15/Qn16 of theswitching circuit 341 to turn on, and only the switching circuit 341 isenabled. The potential difference on the intermediate section of the bitline pair BL1 causes the n-channel enhancement type switchingtransistors Qn17 and Qn18 to turn on and off, and the data line DL1 iselectrically connected through the n-channel enhancement type switchingtransistors Qn15 and Qn17 to the discharging line DSC. However, then-channel enhancement type switching transistor Qn18 isolates the dataline DL2 from the discharging line DSC. As a result, the current flowsthrough the switching circuit 341, the discharging line DSC and then-channel enhancement type discharging transistor Qn32 to the groundline GND, and the potential level on the data line DL1 reaches a voltagelevel given through a proportional distribution between theon-resistances of the field effect transistors Qp21, Qn15, Qn17 andQn32. On the other hand, the potential level on the other data line DL2is maintained, and the potential difference on the bit line pair BL1 istransferred to the data lines DL1 and DL2.

The output circuit 36 produces the output data signal Dout indicative ofthe data bit stored in the memory cell MB11 from the potentialdifference between the data lines DL1 and DL2.

Upon production of the output data signal Dout, the access cycle entersinto the second period T2 at time t3, and the potential control signalCV is recovered from the high voltage level to the low voltage level.Then, the n-channel enhancement type discharging transistor Qn32 turnsoff, and the discharging line DSC is recovered to the voltage levelhigher than the ground voltage level by the threshold Vth of then-channel enhancement type discharging transistor Qn31. Although thecurrent continuously flows from the data line DL1 through the n-channelenhancement type discharging transistor Qn31 into the ground line GND,the potential level on the data line DL1 is slightly lifted, and thecurrent consumption I is decreased as shown.

The potential control signal CV is maintained at the low voltage leveluntil the next access cycle starts at time t4.

As will be appreciated from the foregoing description, the potentialcontrol circuit 37 according to the present invention changes the amountof current flowing into the ground line GND, and the dynamic randomaccess memory device improves the current consumption. The switchingcircuit is enabled as early as that of the prior art, and the accessspeed is not prolonged.

Although the particular embodiment of the present invention has beenshown and described, it will be obvious to those skilled in the art thatvarious changes and modifications may be made without departing from thespirit and scope of the present invention. For example, the potentialcontrol circuit 37 may be replaced with a variable resistor or anotherappropriate circuit with variable in resistance.

What is claimed is:
 1. A semiconductor memory device comprising:a) aplurality of addressable memory cells for storing data bits; b) aplurality of pairs of first data lines selectively coupled to saidplurality of addressable memory cells; c) a first addressing system forselectively connecting said plurality of addressable memory cells tosaid plurality of pairs of first data lines; d) second data lines pairedwith each other; e) a charging circuit coupled to said second data linesfor supplying current thereto; f) a discharging line for dischargingsaid current; g) a second addressing system having a plurality ofswitching circuits coupled in parallel between said second data linesand said discharging line, one of said plurality of switching circuitsbeing responsive to a data bit on one of said plurality of pairs offirst data lines for selectively connecting said second data lines tosaid discharging line, thereby transferring said data bit to said seconddata lines in the form of potential difference; h) an interfaceresponsive to said data bit on said second data lines for producing adata signal; and i) a current control means operative to increase thecurrent flowing from said discharging line to a voltage source forenlarging the potential difference between said second data lines beforesaid interface produces said data signal and to decrease said currentafter completion of the production of said data signal, said currentcontrol means including i-1) a diode coupled between said dischargingline and said voltage source; and i-2) a switching transistor coupledbetween said discharging line and said voltage source in parallel tosaid diode, and responsive to a control signal so as to provide acurrent path before said interface produces said data signal, saidcontrol signal being changed to an inactive level after said completionof the production of said data signal so that said switching transistorturns off.
 2. The semiconductor memory device as set forth in claim 1,in which said diode is implemented by a field effect transistor having asource-to-drain path coupled between said discharging line and saidvoltage source, a gate electrode of said field effect transistor beingcoupled to said discharging line.
 3. The semiconductor memory device asset forth in claim 1, in which said plurality of addressable memorycells are a random access type for storing the data bits in the form ofelectric charges.
 4. The semiconductor memory device as set forth inclaim 3, further comprisingj) a plurality of sense amplifier circuitsrespectively associated with said plurality of pairs of first data linesfor rapidly developing potential differences indicative of the data bitson said plurality of pairs of first data lines.
 5. The semiconductormemory device as set forth in claim 4, in which each of said pluralityof pairs of first data lines is split into a first section coupled tofirst memory cells selected from said plurality of addressable memorycells, a second section coupled to second memory cells selected fromsaid plurality of addressable memory cells and a third section providedbetween said first section and said second section and coupled to one ofsaid sense amplifier circuits and one of said switching circuits,saidsemiconductor memory device further comprising: k) a first transfer gatearray coupled between the first sections of said plurality of pairs offirst data lines and the third sections of said plurality of pairs offirst data lines, and responsive to a first gate control signal forelectrically connecting said first sections to said third sections; andl) a second transfer gate array coupled between the second sections andsaid third sections, and responsive to a second gate control signal forelectrically connecting second sections to said third sections, one ofsaid first gate control signal and said second gate control signal beingchanged to an active level in each data access.